AVR orthogonality

Even though the AVR instruction set is relatively regular, it is not orthogonal:
- Pointer registers X, Y, Z have addressing capabilities that are different from each other.
- Register File locations 0...15 have different addressing capabilities than RF locations 16...31.
- IO locations 0 to 31 have different addressing capabilities than IO locations 32 to 63.
- CLR affects flags, while SER does not, even though they seem to be complementary intructions (set all bits to 0 and respectively to 1).
- opcodes 0x95C8 and 0x9004 do exactly the same thing (LPM).