Logic synthesis

Logic synthesis is a process by which algorithmic descriptions of circuits are turned into a design for electronic hardware of some nature. Common examples of this process include synthesis of HDLs, including VHDL and Verilog. Some tools can generate bitstreams for programmable logic devices such as PAL or GAL devices, or FPGAs, while others target the creation of ASICs.

Examples of software tools for logic synthesis are Design Compiler from Synopsis and the humorously named BuildGates, from Cadence Design Systems.

Logic synthesis is one aspect of electronic design automation.